1. Field of the Invention
The invention relates generally to a device and method of determining the value and location of a decoupling capacitance to be added during the design and layout of a semiconductor circuit to optimally reduce dynamic supply voltage fluctuations during circuit operation at high frequency.
2. Description of the Related Art
As the design and layout of semiconductor circuits, or microcircuits, or chips, become more complex, and in particular, as there is an increase in complexity of very large scale integration (VLSI) layout, an increase in operational frequency and the use of supply voltage scaling, there is an ever increasing need to remove or reduce undesired noise from the semiconductor circuit design. A chip's power distribution network is a major noise source as the fluctuations in supply voltage due to the parasitic resistance, inductance and capacitance in the network alter signals' voltage levels and can cause malfunctioning of the chip's circuits. Designing a robust power distribution network for low dynamic voltage fluctuations has become a challenging task. Extremely dense and complex circuit layouts for high frequency operation necessitate reduction of these undesired noise levels, especially at some sensitive parts of circuits such as clock generators and analog circuits. In general, it is important to improve the voltage fluctuations of all critical areas (known as “hot spots”) of a semiconductor circuit layout.
Static voltage drop (also commonly known as “IR drop”) is usually addressed through increased metallization (reduction of resistance), pad placement, topology optimization and power-density-aware “floor planning.” However, the chief technique for limiting dynamic voltage fluctuations is to place decoupling capacitors (known as “decaps”, in an abbreviated manner) close to problem hot spots. But, as the fabrication process progresses up the technology nodes ladder, and increased wire resistance aggravates the supply noise problem, sufficient decoupling capacitance needs to be added to the power network. Problematically, the high leakage current in these technology nodes discourages the addition of abundant decoupling capacitance. For these reasons, dynamic supply noise needs to be addressed with a minimum amount of decap added in an optimal manner.
As understood in the art, decap budgeting and placement is a non-linear optimization problem. Several sensitivity-based techniques have been proposed whereby a sensitivity-based nonlinear quadratic program uses a compressed piecewise linear form to store adjoint sensitivity. In another proposed method in the art, the conjugate gradient (CG) method is merged with adjoint sensitivity heuristic to speed up the sensitivity calculation of the optimization solution. In another method known in the art, the problem size is reduced using the geometric multigrid concept and then by using a sequential quadratic program on the reduced grid. Its application is thus limited to regular mesh structures. In another known concept, a divide-and-conquer technique is used to reduce the size of the sensitivity-based optimization. A further known method solves the nonlinear optimization through a sequence of linear programming methods. Sensitivities to decaps are used as linear constraints in that optimization. All these known methods, concepts and techniques, however, are problematic. For example, many require calculation of sensitivities with respect to decoupling capacitance location.
Further complicating the problem, these techniques add decap and recompute sensitivity in an iterative procedure. As the complexity of one adjoint sensitivity computation is the same as one transient analysis, the iterative nonlinear optimization procedure becomes quite expensive and time consuming. In addition, the adjoint sensitivity calculation typically needs to store waveforms at every node in both the original and the adjoint networks, which may exhaust the memory resource for large networks.
Several charge-based decap estimation techniques have also been proposed in the art in the context of power supply noise-aware floor planning. An approximate lumped decoupling capacitance is estimated for each floor plan module, with an assumption that the original voltage of decoupling capacitance is a perfect VDD/GND. However, the parasitic capacitance and existing decap value are not considered in these methods, which causes inaccuracies.